# CODE with Redstone

## Mar 31, 2019 14:42 · 562 words · 3 minutes read

In the last post we discussed how to make basic gates in Minecraft using redstone. This post will match up with Chapter 12, in which we’ll build a full adder out of two half adders.

This looks complicated initially, but it’s very simple and easily translates from any half adder circuit diagram. A half adder takes two inputs. It `XOR`s the inputs to generate a sum bit (S) and `AND`s the inputs to generate a carry bit ©.

Our two inputs are on the left side (the levers). They branch upwards into and `AND` gate immediately, which results in C. Therefore the rest of the circuit must be the XOR gate. XOR gates are a little complicated, they are made out of

1. an `OR` gate
2. a `NAND` gate
3. the `AND` of the results of 1 and 2

We can see in the middle of the circuit is our `OR` gate for the `XOR`. On the very bottom of the circuit, we have a familiar and gate. Notice that at the very bottom right corner, there are two inverters in series. The first inverter in that series is the last component required to complete the `AND` gate. The second inverter turns the `AND` into a `NAND`.

Finally the results of the `OR` and the `NAND` are fed into another `AND` gate.

Both of the wires then proceed to the top center where we have two redstone lamps. The lamp on the left is the carry bit C. The lamp on the right is the sum bit S.

If you are following along (or better yet building along!) take a moment to convince yourself that this does implement half addition correctly. It may help to draw a truth table for one or more sub components.

This circuit includes the half adder from before and another half adder. The redstone lamp near the middle of the circuit is the carry bit C from our first half adder. The wire running near the bottom middle is the sum bit from the first half adder. These two signals swamp places in the center of the circuit with the carry bit running down to be `OR`d with the carry bit from half adder #2 and the sum bit from the half adder #1 being used as the input signal to half adder #2.